The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a column decoder array.
In general, the semiconductor memory device adopts a plurality of banks capable of independent data access. And, a row decoder, a column decoder, a read driver, and a write driver, etc., are provided per each bank so that the cells of the corresponding banks can be accessed and at the same time, the transfer of data between the cells and the input/output pad is formed by means of the driving therebetween.
For example, referring to structures of 4 banks BA_HL, BA_HR, BA_LL and BA_LR of FIG. 1, two banks BA_HL and BA_HR and two banks BA_LL and BA_LR are arranged on both sides of a global input/output line GIO.
And, two row decoder arrays Y-DEC Array for driving each bank BA_HL and BA_HR are arranged between the bank (for example, BA_HL) and the bank (for example, BA_HR).
Also, a column decoder array Y-DEC Array for selecting the corresponding memory cell and a data input/output array DATA I/O Array for reading or writing the data of the selected cell are arranged between the bank (for example, BA_HL) and the global input/output line GIO, and between the bank (for example, BA_LL) and the global input/output line GIO, respectively, as a column select signal transferred from the respective column select signal lines YI_HL and YI_LL.
At this time, the data input/output array DATA I/O Array comprises a write driver WDRV transferring data provided from the global input/output line GIO to a local input/output line (for example, LIO_HL) in a write operation and a read driver ISOA transferring data provided from the local input/output line LIO_HL to the global input/output line GIO in a read operation, wherein the drivers are formed in multiple pairs.
As described above, in the prior art the row decoder array Y-DEC Array, the column decoder array Y-DEC Array, and the data input/output array DATA I/O Array, etc., are arranged per the banks BA_HL, BA_HR, BA_LL, and BA_LR so to control data access.
However, in this case, since a row decoder array X-DEC Array, a column decoder array Y-DEC Array, and a data input/output array DATA I/O Array should be basically arranged, one for each of the banks, it originally has any limitation of efficiently using or minimizing the area.
Also, four data can be output at a time from one bank (for example, BA_HL) with one word line and one column select signal line YI_HL, and in the case of a 8 bit prefetch, 128 data are output from one bank in a x16 structure at the same time so that a total of 32 column decoders are required. In other words, there is a problem that as the number of the data processed at one time increases, the number of the column decoder increases.
In order to reduce the number of the column decoder, as show in FIG. 2, the prior art proposes a structure dividing one bank into two parts BA_U and BA_D and stacking them.
In other words, the semiconductor memory device in the prior art is constituted so that the data of the cells selected by means of one column select signal line YI extended from the column decoder array Y-DEC Array and two word lines WL_U and WL_D extended from the row decoder (not shown) are divided by 4 bits, respectively, to be transferred to the local input/output lines LIO_U and LIO_D, respectfully.
However, in the stack bank structure as shown in FIG. 2, since it takes an extended amount of time when the column select signal provided from the column decoder array Y_DEC Array is transferred to the corresponding cell of the bank BA_U rather than when it is transferred to the corresponding cell of the bank BA_D. Accordingly, there is a limit in reducing the loading of the column select signal and the operation speed.
Also, as the semiconductor memory device becomes a relatively large-capacity device, the capacity required for each bank becomes large, and as the capacity of the bank becomes large, the length of the local input/output line LIO_U coupled to the upper bank BA_U becomes long, causing a problem that the loading may increase.
Further, if the length of the local input/output line LIO_U becomes long, there are problems that arise that are associated with the size of the write driver and the read driver IOSA for driving it becomes large so that current consumption may increase and the area occupied by the data input/output device array DATA I/O Array in the semiconductor memory device may increase.